Designing a Student-Etch-Friendly H-Bridge for NERC (NUST)

Engineering case study by mfaseehuddin

Brief

I was assigned to design, develop, and engineer a full H-bridge motor driver for the upcoming NERC competitions at NUST. The constraints were unusual but clear: the PCB had to be single-layer and student-etched, which ruled out dense layouts, tiny packages, and fancy multilayer routing. Reliability, reworkability, and clear testability were non-negotiable.

Context & Requirements

• Drive a brushed DC motor bidirectionally with PWM.

• Survive student abuse (miswiring, stall events, hot swaps).

• Prefer through-hole or large packages for easy solder/repair.

• Keep BOM simple and locally sourceable.

• Respect single-layer routing, generous clearances, and wide power traces for etching.

Architecture Choices & Iteration

I iterated across several high-/low-side driver ICs (IR2104/IR2101 family) before settling on the IR2110 gate-driver. Reasons:

• Separate HO/LO outputs with VB/VS floating high-side supply make bootstrap design straightforward.

• DIP-14 package simplifies hand assembly and repair versus SOIC.

• Clean logic interface (HIN/LIN/SD) decouples MCU timing from power stage. Schematic

Final Design Overview

• Power stage: N-channel MOSFET H-bridge based on IRF540N devices (through-hole), fast recovery diodes (UF4007) for flyback/current steering, and gate resistors tuned for a safe rise/fall compromise.

• Driver: IR2110PBF (DIP-14) with bootstrap cap across VB–VS, separate VCC for gate drive, and VDD for logic domain.

• Regulation & I/O: LM7805 linear regulator to derive 5 V logic; battery input via XT60 connector; screw/jumper headers for motor and logic lines. Schematic

Key callouts visible in the schematic: IRF540N devices (Q1–Q4), UF4007 diodes (D2/D3/D5/D6), IR2110 pins (HIN/LIN/HO/LO/VB/VS/VCC/VDD), LM7805 regulator, XT60-M input, and motor/signal headers. Schematic

PCB for a Single-Layer, Etch-by-Students Process

I laid out the board as single-layer with wide copper pours on power nets, short gate loops, and clear thermal paths from MOSFETs to copper. All high-current runs are fat and straight; signal routes cross power minimally and hug a reference return. Component footprints are spacious and labeled for quick bench debugging. The board is documented as HBridge Rev2 (PCB v11). PCB v11

Layout tactics that paid off

• Star-ish returns: motor current returns kept away from logic ground until a single join near the driver COM.

• Bootstrap practicality: kept VB–VS loop tight and adjacent to the high-side MOSFET to reduce ringing.

• Silkscreen as instruction: explicit net labels and orientation marks to help peer teams assemble correctly.

• Probe points: added pads on HIN/LIN/SD/HO/LO/VS/VB for scope hooks without risking slips on SOIC pins.

Protection & Reliability Considerations

• UF4007 diodes provide robust flyback paths; their recovery is adequate for the intended PWM range.

• Gate resistors curb dV/dt and ringing; values biased for reliability over absolute switching loss.

• Decoupling near VCC/VDD and across VB–VS stabilizes both driver domains.

• Input sanity via SD (shutdown) line lets firmware enforce deadtime and fault handling at the logic layer. Schematic

Build, Bring-Up, and Test

1. Stage power first: validated the LM7805 output with the power stage unpopulated.

2. Driver smoke test: populated IR2110 + passives; verified HIN/LIN → HO/LO behavior on a dummy load.

3. Populate half-bridge: measured switching edges, bootstrap refresh under expected duty, then completed the full H-bridge.

4. Motor tests: stepped from low duty to competition PWM, checked thermal behavior, and verified no cross-conduction (scope on VS/HO/LO).

5. Abuse tests: rapid direction changes, stall intervals in short bursts, connector hot-plug checks.

(Schematic pin/test points and headers aided every phase above.) Schematic

What I’d Improve Next

• Add optional RC snubbers per switch node footprint for teams facing noisier harnesses.

• Provide a shunt + amp footprint for in-line current telemetry to aid firmware current limiting.

• Break out a logic-level variant (e.g., gate drive derated for smaller motors) using the same PCB to support multiple NERC categories.

• Panelize a test coupon on the same FR-4 for etch calibration.

Outcome

A robust, IR2110-based H-bridge that balances performance with manufacturability under student-etch, single-layer constraints—easy to build, easy to probe, and reliable on the competition bench. The design package includes the complete schematic and PCB v11 layout used for fabrication and testing. Schematic PCB v11